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0.12
91807b03
·
Implement the DSP primitive. (#239)
·
Mar 31, 2024
0.11.1
f43a0b7e
·
Merge pull request #230 from yrabbit/make-bits
·
Feb 09, 2024
0.10.0
a7576993
·
Add 20k devices to readme (#209)
·
Dec 03, 2023
0.9.1
cff0cd80
·
Merge pull request #199 from yrabbit/clk
·
Sep 18, 2023
0.9.0
180dfef0
·
Modify CI to generate Himbaechel bases, build and test Himbaechel examples (#197)
·
Sep 02, 2023
0.9.0a1
39c7601d
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Adapting the packer to the alternative P&R (#184)
·
Aug 31, 2023
0.8.3
46ecf0c0
·
Fix OPEN_DRAIN IO attribute (#194)
·
Aug 10, 2023
0.8.2
d6ada5b4
·
python 3.8 support for importlib files api (#189)
·
Aug 03, 2023
0.8.2a1
87131a1f
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use compressed pickle files (#183)
·
Jun 19, 2023
0.8.1
d350cb7c
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Change the IO coding to synthetic (#177)
·
May 29, 2023
0.8
9aede248
·
The ODDR(c) element as part of the IOLOGIC
·
Apr 16, 2023
0.7
7c5bc791
·
Merge pull request #163 from yrabbit/gw1ns-2-1
·
Feb 05, 2023
0.6.2
6d9ca9ca
·
Add support for GW1NR-9C PLL
·
Jan 28, 2023
0.6.1
20af4109
·
Fix the creation of implicit clock wires (#144)
·
Dec 20, 2022
0.6
56468821
·
Add ability to use the clock net for PLL signals (#139)
·
Dec 17, 2022
0.5.1
61b1c142
·
Merge pull request #134 from yrabbit/stage-1
·
Dec 06, 2022
0.5.1a1
368e5183
·
Add information about the functions of the pins.o (#135)
·
Dec 01, 2022
0.5
bbd4b3de
·
Add initial PLL support (#133)
·
Nov 14, 2022
0.4
ec90ea22
·
Add the long wires (#107)
·
Jun 14, 2022
0.3.1
5b93c768
·
Merge pull request #101 from yrabbit/gwalu
·
Apr 04, 2022
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